A 3.5-GHz Digitally-Controlled Open-Loop Fractional-N Frequency Divider in 28-nm CMOS

This paper describes the design and measurement of an open-loop fractional frequency divider implementation. The fractional divider consists of a multi-modulus integer frequency divider (MMD), a sigma-delta modulator (SDM) and a pipelined phase interpolator. The fractional frequency division is achieved with the MMD and the 13-bit SDM toggling the integer division ratio. The resulting signal is then processed by the phase interpolator which significantly reduces the spurs by 22 dB and generates spectrally clean signal with correct output frequency. The prototype is implemented in 28-nm CMOS technology and it operates within input frequency range of 1.9 GHz – 3.5 GHz with fractional division ratio in between 2–3. As an example of the operation, with a setting of an arbitrary division ratio of 2.3164 and input frequency of 2.4 GHz, the output sets correctly to 1.0361 GHz with RMS jitter of 2.1 ps.

Authors:
Cheung Tze Hin, Martelius Mikko, Antonov Yury, Akbar Rehman, Ryynänen Jussi, Pärssinen Aarno, Stadius Kari

Publication type:
A4 Article in conference proceedings

Place of publication:
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 10-21 Oct 2020, Sevilla, Spain

Keywords:
6G Publication

Published:

Full citation:
T. H. Cheung et al., “A 3.5-GHz Digitally-Controlled Open-Loop Fractional-N Frequency Divider in 28-nm CMOS,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180542

DOI:
https://doi.org/10.1109/ISCAS45731.2020.9180542

Read the publication here:
http://urn.fi/urn:nbn:fi-fe202101131686