A fully integrated 4 × 2 element CMOS RF phased array receiver for 5G

This paper presents a fully integrated phased array receiver containing two four element radio frequency (RF) beamforming receivers supporting two multiple-input multiple-output channels. The receivers are designed and fabricated using 45 nm CMOS SOI technology. A 10 bit IQ vector modulator phase shifter (IQVM) is implemented in RF signal paths to control the phase and amplitude of the received signal before combining. Each IQVM provides 360° phase shift control and 17 dB gain variation. An off-chip, simultaneous high-Q impedance matching and bandpass filtering technique for each low-noise amplifiers is presented using non-uniform transmission line segments. Measured downconversion gain at 100 MHz intermediate frequency and noise figure (NF) of a single path are 23 and 5.4 dB, respectively, giving estimated 3.4 dB NF for a single element when simulated PCB and matching losses are taken into account. 1 dB compression point and Input third-order intercept point (IIP3) are − 37 and − 28 dBm, respectively. Each four-element receiver consumes 486 mW DC power from 1.2 V power supply. Total area of two receivers is 5.69 mm².

Shaheen Rana A., Akbar Rehman, Sethi Alok, Aikio Janne P., Rahkonen Timo, Pärssinen Aarno

Publication type:
A1 Journal article – refereed

Place of publication:

5G, beamforming, CMOS SOI, Input matching, LNA, Mixer, mmWave, Phase shifter, Phased Array, Receiver, RF, Vector modulator, Wireless communication

29 June 2018

Full citation:
Shaheen, R.A., Akbar, R., Sethi, A. et al. Analog Integr Circ Sig Process (2018). https://doi.org/10.1007/s10470-018-1251-0


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