In this contribution, it is proposes to limit the quantization search space of a successive approximation analog-to-digital converter through an analytic derivation of maximum possible sample-to-sample variation. The presented example design of the proposed ADC is an 8-bit 1MS/s ADC with SAR logic customized to incorporate this priori information while no modification has been required to the analog circuitry. In comparison to conventional SAR conversion, the proposed tracking approach yields significant reduction in total power consumption in oversampling mode. The power savings are due to the reduced number of SAR cycles, and voltage variation minimization across DAC capacitors. The design is reconfigurable both to conventional SAR sampling and the proposed tracking scheme. The approach is attractive for SAR ADCs embedded in very low power micro-controllers.
Safarpour Mehdi, Inanlou Reza, Silvén Olli, Rahkonen Timo, Shoaei Omid
A4 Article in conference proceedings
Place of publication:
2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA) 18-20th September 2019, Poznań, Poland
19 December 2019
M. Safarpour, R. Inanlou, O. Silvén, T. Rahkonen and O. Shoaei, “A Reconfigurable Dual-Mode Tracking SAR ADC without Analog Subtraction,” 2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), Poznan, Poland, 2019, pp. 28-32. doi: 10.23919/SPA.2019.8936832
Read the publication here: