Analysis and implementation of sdf radix-2 fft processor using verilog hardware description language

This paper will study a novel system on chip (SoC) design for fast Fourier transform (FFT) module. We first explain the role and position of FFT module in a digital intelligent system. Then, the discrete Fourier transform (DFT) and decimation in frequency (DIF) Radix-2 butterfly FFT algorithm is explained in detail, mathematically. In addition, the analysis of a simple pipeline FFT processor and a single-path delay feedback pipeline FFT processor based on SDF Radix-2 algorithm are discussed. Finally, the implementation and verification of proposed FFT processor are performed VERILOG hardware description language (HDL).

Authors:
Lai Phuong H., Hoang Manh, Tran Viet Q., Nguyen Tung V., Truong Thien V., Nguyen Phong H.

Publication type:
A1 Journal article – refereed

Place of publication:

Keywords:
Fourier transform, FPGA, Pipeline processor, System on Chip design, VERILOG HDL

Published:

Full citation:
H. Lai, P. (2020). Analysis and implementation of SDF Radix-2 FFT processor using VERILOG Hardware Description Language. International Journal of Advanced Trends in Computer Science and Engineering, 9(4), 5185–5189. https://doi.org/10.30534/ijatcse/2020/144942020

DOI:
https://doi.org/10.30534/ijatcse/2020/144942020

Read the publication here:
http://urn.fi/urn:nbn:fi-fe2020112092225