In this paper, we implement a high throughput multiple-input multiple-output (MIMO) detector for single-carrier frequency-division multiple access (SC-FDMA) base station. High-level Synthesis (HLS) tool is used for implementing the algorithm on Xilinx Virtex and Zynq FPGAs. First, we compare the throughput performance and power consumption results of the different implementations. Second, we evaluate the quality of the results by comparing the HLS results to handwritten register-transfer level (RTL) implementations. In conclusion, the HLS tools have evolved into applicable implementation tools. Furthermore, the possible slight losses in the performance or design complexity with the HLS design method could be counteracted by choosing a higher category FPGA.
Hänninen Tuomo, Yadegar Amin Hamid, Juntti Markku
A4 Article in conference proceedings
Place of publication:
Conference Record of the Fifty-Second Asilomar Conference on Signals, Systems & Computers
T. Hänninen, H. Y. Amin and M. Juntti, “Base Station MIMO Detector Algorithm Implementations,” 2018 52nd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 2018, pp. 195-198. doi: 10.1109/ACSSC.2018.8645429
Read the publication here: