Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process

This paper concerns with the design of multi-stacked CMOS millimeter-wave power amplifiers suitable for phased array front-end applications using triple-well process. The parasitics posed by the triple-well technique are studied and compensated using negative capacitance technique for proper operation. The design technique is evaluated using TSMC 28nm CMOS process at 28GHz operating frequency as a candidate operating band for 5G systems. The results illustrate a power gain of 25dB, 22dBm saturated power, and a maximum 38% PAE along with superior phase alignment between stacks.

Authors:
Montaseri Mohammad Hassan, Vuohtoniemi Risto, Aikio Janne, Rahkonen Timo, Pärssinen Aarno

Publication type:
A4 Article in conference proceedings

Place of publication:
2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Keywords:
5G, CMOS integrated circuits, deep n-well process, millimeter-wave integrated circuits, mm-wave power amplifiers, Phased Array, stacked transistor, triple-well process

Published:
13 December 2018

Full citation:
M. H. Montaseri, R. Vuohtoniemi, J. Aikio, T. Rahkonen and A. Pärssinen, “Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process,” 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, 2018, pp. 1-5. doi: 10.1109/NORCHIP.2018.8573452

DOI:
https://doi.org/10.1109/NORCHIP.2018.8573452

Read the publication here:
http://urn.fi/urn:nbn:fi-fe201902134755