Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI

Two mmWave frequency dividers were designed, manufactured and measured using static current mode logic divider topology on 45nm CMOS PD-SOI technology. Dividers differ by flip-flop load, first divider uses resistive loads and second divider active PMOS loads. Achieved output referred frequency ranges cover 13—22GHz on the first divider and 8—23GHz on the second divider. Both dividers occupy small areas of $0.002mathrm{mm}^{2}$ and $0.0017mathrm{mm}^{2}$ respectively and dissipate only 10.3mW and 11mW from 1V supply. The broad tuning range, moderate speed, small area and I/Q output phases make this divider architecture an attractive option for sliding-IF transceiver topologies operating up to 69GHz carrier frequency and enable operation of PLL’s up to 46GHz.

Authors:
Hietanen Mikko, Aikio Janne, Sethi Alok, Akbar Rehman, Rahkonen Timo, Pärssinen Aarno

Publication type:
A4 Article in conference proceedings

Place of publication:
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) 29-30 Oct 2019 Helsinki, Finland

Keywords:
CML, CMOS, Frequency Divider, mmWave, SOI, Static Flip-flop

Published:
30 October 2019

Full citation:
M. Hietanen, J. Aikio, A. Sethi, R. Akbar, T. Rahkonen and A. Pärssinen, “Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI,” 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, 2019, pp. 1-4. doi: 10.1109/NORCHIP.2019.8906899

DOI:
https://doi.org/10.1109/NORCHIP.2019.8906899

Read the publication here:
http://urn.fi/urn:nbn:fi-fe2019121748475