This paper proposes how to define the optimum number of stacked transistors in a multi-stacked CMOS power amplifier (PA) topology, based on several physical as well as circuit design aspects. Starting with a systematic concept, the analysis then goes through the relevance of transistor transconductance, aspect ratio, parasitics, operating frequency, and the number of transistor stages in a pentagonal trade-off concept. While this is done based on theoretical circuit analysis, the results, then, are evaluated using simulations based on 45nm CMOS technology.
Montaseri Mohammad Hassan, Aikio Janne, Rahkonen Timo, Pärssinen Aarno
A4 Article in conference proceedings
Place of publication:
2018 IEEE International Symposium on Circuits and Systems (ISCAS). 27-30 May 2018, Florence, Italy
M. H. Montaseri, J. Aikio, T. Rahkonen and A. Pärssinen, “Optimum Number of Transistors in Stacked CMOS Millimeter-Wave Power Amplifiers,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4. doi: 10.1109/ISCAS.2018.8351160
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