Optimum Number of Transistors in Stacked CMOS Millimeter-Wave Power Amplifiers

This paper proposes how to define the optimum number of stacked transistors in a multi-stacked CMOS power amplifier (PA) topology, based on several physical as well as circuit design aspects. Starting with a systematic concept, the analysis then goes through the relevance of transistor transconductance, aspect ratio, parasitics, operating frequency, and the number of transistor stages in a pentagonal trade-off concept. While this is done based on theoretical circuit analysis, the results, then, are evaluated using simulations based on 45nm CMOS technology.

Authors:
Montaseri Mohammad Hassan, Aikio Janne, Rahkonen Timo, Pärssinen Aarno

Publication type:
A4 Article in conference proceedings

Place of publication:
2018 IEEE International Symposium on Circuits and Systems (ISCAS). 27-30 May 2018, Florence, Italy

Keywords:
CMOS, millimeter-wave integrated circuits, millimeter-wave power amplifiers, multi-stacked topology

Published:

Full citation:
M. H. Montaseri, J. Aikio, T. Rahkonen and A. Pärssinen, “Optimum Number of Transistors in Stacked CMOS Millimeter-Wave Power Amplifiers,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4. doi: 10.1109/ISCAS.2018.8351160

DOI:
https://doi.org/10.1109/ISCAS.2018.8351160

Read the publication here:
http://urn.fi/urn:nbn:fi-fe201902134733