Real-Time Quantile-Based Estimation of Resource Utilization on an FPGA Platform Using HLS

Hardware accelerated modules that can continuously measure/analyze resource (frequency channels, power, etc.) utilization in real-time can help in achieving efficient network control, and configuration in cloud managed wireless networks. As utilization of various network resources over time often exhibits broad and skewed distribution, estimating quantiles of metrics to characterize their distribution is more useful than typical approaches that tend to focus on measuring average values only. In this paper, we describe the development of a real-time quantile-based resource utilization estimator module for wireless networks. The intensive processing tasks run on the FPGA, while the command and control runs on an embedded ARM processor. The module is implemented by using high level synthesis (HLS) on a Xilinx’s Zynq-7000 series all programmable system on chip board. We test the performance of the implemented quantile estimator module, and as an example, we focus on forecasting congestion with real frequency channel utilization data. We compare the results from the implemented module against the results from a theoretical quantile estimator. We show that with high accuracy and in real time, the implemented module can perform quantile estimation and can be utilized to perform forecasting of congestion in wireless frequency spectrum utilization.

Ganewattha Chanaka, Khan Zaheer, Lehtomäki Janne J., Matinmikko-Blue Marja

Publication type:
A1 Journal article – refereed

Place of publication:

5G, channel resource allocation, forecasting, FPGA, generalized extreme value theory, high level synthesis, URLLC, wireless channel congestion, Xilinx, ZedBoard

2 March 2020

Full citation:
C. Ganewattha, Z. Khan, J. J. Lehtomäki and M. Matinmikko-Blue, “Real-Time Quantile-Based Estimation of Resource Utilization on an FPGA Platform Using HLS,” in IEEE Access, vol. 8, pp. 43301-43313, 2020, doi: 10.1109/ACCESS.2020.2977760


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