Transport Triggered Array Processor for Vision Applications

Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, ultra-low-leakage processes are employed in fabrication. Those limit the clocking rates significantly, reducing the computing throughputs of individual cores. In this contribution we explore compensating for the substantial computing power needs of a vision application using massive parallelism. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.

Authors:
Safarpour Mehdi, Hautala Ilkka, Bordallo López Miguel, Silvén Olli

Publication type:
A4 Article in conference proceedings

Place of publication:
Embedded Computer Systems: Architectures, Modeling, and Simulation 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings

Keywords:
Binary Patterns, computer vision, Embedded systems, Massive processing arrays Internet-of-Things

Published:
8 August 2019

Full citation:
Safarpour M., Hautala I., Bordallo López M., Silvén O. (2019) Transport Triggered Array Processor for Vision Applications. In: Pnevmatikatos D., Pelcat M., Jung M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019. Lecture Notes in Computer Science, vol 11733. Springer, Cham, https://doi.org/10.1007/978-3-030-27562-4_26

DOI:
https://doi.org/10.1007/978-3-030-27562-4_26

Read the publication here:
http://urn.fi/urn:nbn:fi-fe2019093030526